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DS1225AB/AD 64k Nonvolatile SRAM
www.dalsemi.com
FEATURES
10 years minimum data retention in the absence of external power Data is automatically protected during power loss Directly replaces 8k x 8 volatile static RAM or EEPROM Unlimited write cycles Low-power CMOS JEDEC standard 28-pin DIP package Read and write access times as fast as 70 ns Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time Full 10% VCC operating range (DS1225AD) Optional 5% VCC operating range (DS1225AB) Optional industrial temperature range of -40C to +85C, designated IND
PIN ASSIGNMENT
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
28-Pin ENCAPSULATED PACKAGE 720-mil EXTENDED
PIN DESCRIPTION
A0-A12 DQ0-DQ7 CE WE OE VCC GND NC - Address Inputs - Data In/Data Out - Chip Enable - Write Enable - Output Enable - Power (+5V) - Ground - No Connect
DESCRIPTION
The DS1225AB and DS1225AD are 65,536-bit, fully static, nonvolatile SRAMs organized as 8192 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAMs can be used in place of existing 8k x 8 SRAMs directly conforming to the popular bytewide 28-pin DIP standard. The devices also match the pinout of the 2764 EPROM and the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
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DS1225AB/AD
READ MODE
The DS1225AB and DS1225AD execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 13 address inputs (A0 -A12) defines which of the 8192 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS1225AB and DS1225AD execute a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1225AB provides full functional capability for VCC greater than 4.75 volts and write protects by 4.5 volts. The DS1225AD provides full-functional capability for VCC greater than 4.5 volts and write protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protect themselves, all inputs become "don't care," and all outputs become highimpedance. As VCC falls below approximately 3.0 volts, the power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1225AB and 4.5 volts for the DS1225AD.
FRESHNESS SEAL
Each DS1225 is shipped from Dallas Semiconductor with the lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level of greater than VTP , the lithium energy source is enabled for battery backup operation.
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DS1225AB/AD
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature
-0.3V to +7.0V 0C to 70C; -40C to +85C for IND parts -40C to +70C; -40C to +85C for IND parts 260C for 10 seconds
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER DS1225AB Power Supply Voltage DS1225AD Power Supply Voltage Logic 1 Logic 0 SYMBOL VCC VCC VIH VIL MIN 4.75 4.50 2.2 0.0 TYP 5.0 5.0 MAX 5.25 5.5 VCC +0.8
(TA: See Note 10)
UNITS V V V V NOTES
DC ELECTRICAL CHARACTERISTICS
PARAMETER Input Leakage Current I/O Leakage Current CE > VIH< VCC Output Current @ 2.4V Output Current @ 0.4V Standby Current CE =2.2V Standby Current CE =VCC -0.5V Operating Current tCYC=200 ns (Commercial) Operating Current tCYC=200 ns (Industrial) Write Protection Voltage (DS1225AB) Write Protection Voltage (DS1225AD) SYMBOL IIL MIN -1.0
(VCC =5V 5% for DS1225AB) (TA: See Note 10) (VCC =5V 10% for DS1225AD)
TYP MAX +1.0 UNITS A A NOTES
IIO IOH IOL ICCS1 ICCS2 ICC01 ICC01 VTP VTP
-1.0 -1.0 2.0 5.0 3.0
+1.0
10.0 5.0 75 85
mA mA mA mA mA mA V V
4.50 4.25
4.62 4.37
4.75 4.5
CAPACITANCE
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN TYP 5 5 MAX 10 10
(TA =25C)
UNITS pF pF NOTES
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DS1225AB/AD
AC ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL
(VCC =5V 5% for DS1225AB) (TA: See Note 10) (VCC =5V 10% for DS1225AD)
DS1220AB-85 DS1220AD-85 MIN MAX 85 85 45 85 UNITS NOTES
Read Cycle Time Access Time OE to Output Valid CE to Output Valid OE or CE to Output Active Output High Z from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High Z from WE Output Active from WE Data Setup Time Data Hold Time
tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2
DS1225AB-70 DS1225AD-70 MIN MAX 70 70 35 70 5 25 5
5 30 5 85 65 0 0 10
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
5 5
70 55 0 0 10 25 5 30 0 10
3 12 13 5 5 4 12 13
30 5 35 0 10
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DS1225AB/AD
AC ELECTRICAL CHARACTERISTICS (cont'd)
PARAMETER SYMBOL
DS1225AB- 150 DS1225AD- 150 DS1220AB-200 DS1220AD-200
UNITS
NOTES
Read Cycle Time Access Time OE to Output Valid CE to Output Valid OE or CE to Output Active Output High Z from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High Z from WE Output Active from WE Data Setup Time Data Hold Time
tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2
MIN 150
MAX
MIN 200
MAX
150 70 150 5 35 5 150 100 0 0 10 35 5 60 0 10 5 80 0 10 5 200 100 0 0 10 5
200 100 200 35
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
5 5
3 12 13 5 5 4 12 13
35
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DS1225AB/AD
READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
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DS1225AB/AD
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
PARAMETER
(TA : See Note 10)
UNITS s s s ms UNITS years NOTES 11
CE at VIH before Power-Down VCC slew from VTP to 0V VCC slew from 0V to VTP CE at VIH after Power-Up
PARAMETER Expected Data Retention Time
SYMBOL MIN TYP MAX 0 tPD 300 tF 300 tR 2 125 tREC SYMBOL MIN TYP MAX tDR 10
(TA = 25C)
NOTES 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
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DS1225AB/AD
NOTES:
1. WE is high for a read cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. 3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDS are measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output buffers remain in a high-impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high-impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. 9. Each DS1225AB and each DS1225AD has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. 10. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0C to 70C. For industrial products (IND), this range is -40C to +85C. 11. In a power down condition the voltage on any pin may not exceed the voltage on VCC . 12. tWR1 , tDH1 are measured from WE going high. 13. tWR2 , tDH2 are measured from CE going high. 14. DS1225AB and DS1225AD modules are recognized by Underwriters Laboratory (U.L.) under file E99151.
DC TEST CONDITIONS
Outputs Open All Voltages Are Referenced to Ground
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0 - 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns
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DS1225AB/AD
ORDERING INFORMATION
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DS1225AB/AD
DS1225AB/AD NONVOLATILE SRAM, 28-PIN, 720-MIL EXTENDED MODULE
PKG DIM A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN MM J IN. MM K IN. MM 28-PIN MIN MAX 1.520 1.540 38.61 39.12 0.695 0.720 17.65 18.29 0.395 0.415 10.03 10.54 0.100 0.130 2.54 3.30 0.017 0.030 0.43 0.76 0.120 0.160 3.05 4.06 0.090 0.110 2.29 2.79 0.590 0.630 14.99 16.00 0.008 0.012 0.20 0.30 0.015 0.021 0.38 0.53
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